// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  proctrainctrl_reg_offset.h
// Project line  :  IP
// Department    :  
// Author        :  Jason, Edward
// Version       :  .1
// Date          :  2011/11/29
// Description   :  The DDR PHY Controller Block
// Others        :  Generated automatically by nManager V4.2 
// History       :  Jason, Edward 2018/03/19 12:28:13 Create file
// ******************************************************************************

#ifndef __PROCTRAINCTRL_REG_OFFSET_H__
#define __PROCTRAINCTRL_REG_OFFSET_H__

/* ProcTrainCtrl Base address of Module's Register */
#define PHY_Controller_ProcTrainCtrl_BASE                       (0x2000)

/******************************************************************************/
/*                      PHY_Controller ProcTrainCtrl Registers' Definitions                            */
/******************************************************************************/

#define PHY_Controller_ProcTrainCtrl_UC_TRCTRL_REG        (PHY_Controller_ProcTrainCtrl_BASE + 0x0)   /* This register control the mode of retraining sequence. */
#define PHY_Controller_ProcTrainCtrl_UC_TROPCTRL_REG      (PHY_Controller_ProcTrainCtrl_BASE + 0x4)   /* This register provide the fine training step control. Please note that writing to this register may trigger the sub-sequence of training sequence which may conflict the on-going training if any. Thus, the user should not modify this register if currenlty hardware training is on-going. */
#define PHY_Controller_ProcTrainCtrl_UC_DTRSTSP_REG       (PHY_Controller_ProcTrainCtrl_BASE + 0x8)   /* This register provide the partial fine training status requested by the UC_DTRAINCTRL. */
#define PHY_Controller_ProcTrainCtrl_UC_TRSTATUS_REG      (PHY_Controller_ProcTrainCtrl_BASE + 0xC)   /* This register provide retraining status register for micro-controller to monitor if retraining (phy update) required. */
#define PHY_Controller_ProcTrainCtrl_UC_CMDQCTRL_REG      (PHY_Controller_ProcTrainCtrl_BASE + 0x10)  /* This register provide registers for micro-controller to control the Command QUEUE (CMDQ). */
#define PHY_Controller_ProcTrainCtrl_UC_ADDRPH_A_AUC_REG  (PHY_Controller_ProcTrainCtrl_BASE + 0x30)  /* This register provide the ALU control for the ADDR PH delay value. */
#define PHY_Controller_ProcTrainCtrl_UC_ADDRBDL_A_AUC_REG (PHY_Controller_ProcTrainCtrl_BASE + 0x34)  /* This register provide the ALU control for the ADDR BDL delay value. */
#define PHY_Controller_ProcTrainCtrl_UC_CSRBDL_AUC_REG    (PHY_Controller_ProcTrainCtrl_BASE + 0x38)  /* This register provide the ALU control for the CS  BDL delay value. */
#define PHY_Controller_ProcTrainCtrl_UC_WDQPHAUC_REG      (PHY_Controller_ProcTrainCtrl_BASE + 0x40)  /* This register provide the ALU control for the write DQ common phase selection value. */
#define PHY_Controller_ProcTrainCtrl_UC_WDQSPHAUC_REG     (PHY_Controller_ProcTrainCtrl_BASE + 0x48)  /* This register provide the ALU control for the write DQS phase selection value. */
#define PHY_Controller_ProcTrainCtrl_UC_WDQSBDLAUC_REG    (PHY_Controller_ProcTrainCtrl_BASE + 0x4C)  /* This register provide the ALU control for the write DQS BDL delay value. Note that the register also control the oenbdl and wdqsoebdl delay value at the same time. That is, if the ALU is select to do arithmetic operations, these three delay lines will be calculated and udpated at the same time. */
#define PHY_Controller_ProcTrainCtrl_UC_WDLYOP_REG        (PHY_Controller_ProcTrainCtrl_BASE + 0x50)  /* This register provides the operations on the write related delay lines. */
#define PHY_Controller_ProcTrainCtrl_UC_RDQSAUC_REG       (PHY_Controller_ProcTrainCtrl_BASE + 0x80)  /* This register provide the ALU control for the read DQS delay lines. */
#define PHY_Controller_ProcTrainCtrl_UC_RDQSGTXAUC_REG    (PHY_Controller_ProcTrainCtrl_BASE + 0x84)  /* This register provide the ALU control for the read DQS gate TX delay lines. */
#define PHY_Controller_ProcTrainCtrl_UC_RDQSGPHAUC_REG    (PHY_Controller_ProcTrainCtrl_BASE + 0x88)  /* This register provide the ALU control for the read DQS gate phase selection. */
#define PHY_Controller_ProcTrainCtrl_UC_RDQSGBDLAUC_REG   (PHY_Controller_ProcTrainCtrl_BASE + 0x8C)  /* This register provide the ALU control for the read DQS Gate BDL delay value. */
#define PHY_Controller_ProcTrainCtrl_UC_RGDSAUC_REG       (PHY_Controller_ProcTrainCtrl_BASE + 0x90)  /* This register provide the ALU control for the read GDS value. */
#define PHY_Controller_ProcTrainCtrl_UC_RDLYOP_REG        (PHY_Controller_ProcTrainCtrl_BASE + 0x94)  /* This register provides the operations on the read related delay lines. */
#define PHY_Controller_ProcTrainCtrl_UCSWTMODE_REG        (PHY_Controller_ProcTrainCtrl_BASE + 0xA0)  /* This register is for setting S/W training mode */
#define PHY_Controller_ProcTrainCtrl_UCSWTWLDQS_REG       (PHY_Controller_ProcTrainCtrl_BASE + 0xA4)  /* This register is for issuing write DQS in S/W write leveling training */
#define PHY_Controller_ProcTrainCtrl_UC_SWTRLT_REG        (PHY_Controller_ProcTrainCtrl_BASE + 0xA8)  /* S/W training result */
#define PHY_Controller_ProcTrainCtrl_UCSWMRRDATA_REG      (PHY_Controller_ProcTrainCtrl_BASE + 0xAC)  /* SW MRR data for read. */
#define PHY_Controller_ProcTrainCtrl_UCCATCONFIG_REG      (PHY_Controller_ProcTrainCtrl_BASE + 0xB0)  /* CA Training Configuration */
#define PHY_Controller_ProcTrainCtrl_UCPHYDQRESULT_REG    (PHY_Controller_ProcTrainCtrl_BASE + 0xB8)  /* SW CA Training DQ result from PHY */
#define PHY_Controller_ProcTrainCtrl_UCSWCATPATTERN_P_REG (PHY_Controller_ProcTrainCtrl_BASE + 0xBC)  /* SW CA Training pattern for  positive CK edge */
#define PHY_Controller_ProcTrainCtrl_UCFASTGDSRLT0_REG    (PHY_Controller_ProcTrainCtrl_BASE + 0xC4)  /* Fast gate trainning and fast GDS trainning result that can be read by users */
#define PHY_Controller_ProcTrainCtrl_UCFASTGDSRLT1_REG    (PHY_Controller_ProcTrainCtrl_BASE + 0xC8)  /* Fast gate trainning and fast GDS trainning result that can be read by users */
#define PHY_Controller_ProcTrainCtrl_UCFASTGTRLT_REG      (PHY_Controller_ProcTrainCtrl_BASE + 0xCC)  /* Fast gate trainning and fast GDS trainning result that can be read by users */
#define PHY_Controller_ProcTrainCtrl_UCTRKDBG_RDQS_REG    (PHY_Controller_ProcTrainCtrl_BASE + 0xD0)  /* DQS Dynamic Tracking information for debug */
#define PHY_Controller_ProcTrainCtrl_UCTRKDBG_RDQSG0_REG  (PHY_Controller_ProcTrainCtrl_BASE + 0xD4)  /* DQSG Dynamic Tracking information for debug */
#define PHY_Controller_ProcTrainCtrl_UCTRKDBG_RDQSG1_REG  (PHY_Controller_ProcTrainCtrl_BASE + 0xD8)  /* DQSG Dynamic Tracking information for debug */
#define PHY_Controller_ProcTrainCtrl_UCDBG_PHYSTOP_REG    (PHY_Controller_ProcTrainCtrl_BASE + 0xDC)  /* PHY STOP information for debug */
#define PHY_Controller_ProcTrainCtrl_UCDBG_PERBIT0_REG    (PHY_Controller_ProcTrainCtrl_BASE + 0xE0)  /* Perbit tracking information reg 0 for debug */
#define PHY_Controller_ProcTrainCtrl_UCDBG_PERBIT1_REG    (PHY_Controller_ProcTrainCtrl_BASE + 0xE4)  /* Perbit tracking information reg 1 for debug */
#define PHY_Controller_ProcTrainCtrl_UCDBG_PERBIT2_REG    (PHY_Controller_ProcTrainCtrl_BASE + 0xE8)  /* Perbit tracking information reg 2 for debug */
#define PHY_Controller_ProcTrainCtrl_UCDBG_PERBIT3_REG    (PHY_Controller_ProcTrainCtrl_BASE + 0xEC)  /* Perbit tracking information reg 3 for debug */
#define PHY_Controller_ProcTrainCtrl_UCDBG_PERBIT4_REG    (PHY_Controller_ProcTrainCtrl_BASE + 0xF0)  /* Perbit tracking information reg 4 for debug */
#define PHY_Controller_ProcTrainCtrl_UCDBG_PERBIT5_REG    (PHY_Controller_ProcTrainCtrl_BASE + 0xF4)  /* Perbit tracking information reg 5 for debug */
#define PHY_Controller_ProcTrainCtrl_UCDBG_PERBIT6_REG    (PHY_Controller_ProcTrainCtrl_BASE + 0xF8)  /* Perbit tracking information reg 6 for debug */
#define PHY_Controller_ProcTrainCtrl_UCDBG_PERBIT7_REG    (PHY_Controller_ProcTrainCtrl_BASE + 0xFC)  /* Perbit tracking information reg 7 for debug */
#define PHY_Controller_ProcTrainCtrl_UC_WDQNAUC_0_REG     (PHY_Controller_ProcTrainCtrl_BASE + 0x100) /* This register provide the ALU control for the write DQn delay lines. */
#define PHY_Controller_ProcTrainCtrl_UC_WDQNAUC_1_REG     (PHY_Controller_ProcTrainCtrl_BASE + 0x180) /* This register provide the ALU control for the write DQn delay lines. */
#define PHY_Controller_ProcTrainCtrl_UC_RDQNAUC_0_REG     (PHY_Controller_ProcTrainCtrl_BASE + 0x104) /* This register provide the ALU control for the Read DQn delay lines. */
#define PHY_Controller_ProcTrainCtrl_UC_RDQNAUC_1_REG     (PHY_Controller_ProcTrainCtrl_BASE + 0x184) /* This register provide the ALU control for the Read DQn delay lines. */
#define PHY_Controller_ProcTrainCtrl_UC_DTRSTS_0_REG      (PHY_Controller_ProcTrainCtrl_BASE + 0x108) /* This register provide the fine training status requested by the UC_DTRAINCTRL. */
#define PHY_Controller_ProcTrainCtrl_UC_DTRSTS_1_REG      (PHY_Controller_ProcTrainCtrl_BASE + 0x188) /* This register provide the fine training status requested by the UC_DTRAINCTRL. */

#endif // __PROCTRAINCTRL_REG_OFFSET_H__
